
`include "common_header.verilog"

//  *************************************************************************
//  File : redge_ckxing.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2002 MoreThanIP.com, Germany
//  info@morethanip.com
//  Designed by : Daniel Koehler
//  *************************************************************************                    
//  Description: Convert rising edge input signal from input clock domain into 
//               pulse within output clock domain
//  Version    : $Id: redge_ckxing.v,v 1.3 2017/04/18 07:04:31 fb Exp $
//  *************************************************************************

module redge_ckxing (
   reset,
   clk,
   sig,
   reset_clk_o,
   clk_o,
   sig_o);

input   reset; 
input   clk; 
input   sig;            //  pulse or active high input
input   reset_clk_o; 
input   clk_o; 
output  sig_o;          //  always a single clock pulse output


//  Input clock domain
reg     sig_o; 
reg     inlatch; 
wire     in_reg_s1;      //  handshake

//  clk_o domain
wire    out_reg_s1;     //  domain crossing
reg     out_reg_s2;     


//  input clock domain
//  ------------------

always @(posedge reset or posedge clk)
   begin : ind
   if (reset == 1'b 1)
      begin
      inlatch <= 1'b 0;	
      end
   else
      begin
      if (sig == 1'b 1)
         begin
         inlatch <= 1'b 1;	
         end
      else if (in_reg_s1 == 1'b 1 )
         begin
         inlatch <= 1'b 0;	
         end
      end
   end



mtip_xsync  #(1) U_RESYNC_INPUT (

        .data_in        (out_reg_s1),
        .reset          (reset),
        .clk            (clk),
        .data_s         (in_reg_s1));

//  output clock domain
//  -------------------
always @(posedge reset_clk_o or posedge clk_o)
   begin : op
   if (reset_clk_o == 1'b 1)
      begin	
      out_reg_s2 <= 1'b 0;	
      sig_o <= 1'b 0;	
      end
   else
      begin	
      out_reg_s2 <= out_reg_s1;	
//  pulse forming
      if (out_reg_s2 == 1'b 0 & out_reg_s1 == 1'b 1)
         begin
         sig_o <= 1'b 1;	
         end
      else
         begin
         sig_o <= 1'b 0;	
         end
      end
   end


mtip_xsync  #(1) U_RESYNC_OUTPUT (

        .data_in        (inlatch),
        .reset          (reset_clk_o),
        .clk            (clk_o),
        .data_s         (out_reg_s1));

endmodule // module redge_ckxing

